This invention relates to a multiple channel high-speed serial interface, especially in a programmable logic device, in which different channels may have different transmit data rates.
Recently, PLDs have begun to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (10 Gbps Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic. Within each transceiver, the receiver portion typically includes a phase-locked loop (“PLL”), primarily for the purpose of enabling clock data recovery from a received high-speed serial signal. In addition, the central logic typically includes a PLL, primarily for the purpose of generating a transmit clock to be used by the transmitter portion of each of the four transceivers, and in some cases for generating a reference clock for the receiver PLLs.
In many cases, the individual receivers or transmitters in a quad are intended to be used together, for multi-channel reception or transmission of related signals. In such applications, there is no disadvantage in having a common transmit clock generated in the central logic. However, particularly in programmable logic where the use to which a user puts portions of the device may be unexpected, in some applications the individual channels may be used separately, and it may be desirable to be able to use different transmit clocks in the different channels of the quad.